Wafer-Level Testing and Test During Burn-In for Integrated Circuits.
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This...
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| Format: | Electronic eBook |
| Language: | English |
| Published: |
Norwood :
Artech House,
2010.
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| Online Access: |
Full text (MFA users only) |
| ISBN: | 9781596939905 1596939907 9781596939899 1596939893 |
| Local Note: | ProQuest Ebook Central |
| Summary: | Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain. |
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| Physical Description: | 1 online resource (214 pages) |
| Library Staff: | View instance in FOLIO |