Wafer-Level Testing and Test During Burn-In for Integrated Circuits.
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This...
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| Other Authors: | |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Norwood :
Artech House,
2010.
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| Subjects: | |
| Online Access: |
Full text (MFA users only) |
| ISBN: | 9781596939905 1596939907 9781596939899 1596939893 |
| Local Note: | ProQuest Ebook Central |
Table of Contents:
- Wafer-Level Testing and TestDuring Burn-In for Integrated Circuits; Contents; Preface; Acknowledgements; Chapter 1 Introduction; 1.1 BACKGROUND; 1.1.1 System-Level Design-for-Test and Test Scheduling for Core-Based SoCs; 1.1.2 Wafer-Level Test During Burn-In; 1.1.3 Scan Design; 1.2 KEY DRIVERS FORWAFER-LEVEL TEST AND BURN-IN; 1.2.1 Challenges Associated withWafer Sort; 1.2.2 Emergence of KGDs; 1.2.3 WLTBI: Industry Adoption and Challenges; 1.3 WAFER-LEVEL TEST PLANNING FOR CORE-BASED SOCS; 1.4 WAFER-LEVEL DEFECT SCREENING FOR MIXED-SIGNAL SOCS; 1.5 WLTBI OF CORE-BASED SOCS.
- 1.6 POWER MANAGEMENT FOR WLTBI1.7 HOWTHIS BOOK IS ORGANIZED; References; Chapter 2 Wafer-Level Test and Burn-In: Industry Practices and Trends; 2.1 OVERVIEW AND DEFINITIONS; 2.2 STATUS OFWAFER-LEVEL TEST AND WLBI; 2.2.1 Wafer-Level Burn-In; 2.3 DOING BOTH WAFER-LEVEL TEST AND WAFER-LEVEL BURN IN; 2.4 PRACTICAL MATTERS; 2.4.1 Volumes Needed; 2.4.2 Power per Die and perWafer; 2.4.3 Types of Die That Can Be Tested and Burned-In; 2.4.4 Functional Tests Versus Parametric Tests; 2.4.5 Number of Contacts per Die; 2.4.6 Number of Signal Channels Needed; 2.4.7 Single-Pass Versus Multiple Pass.
- 2.4.8 Maximum Force per Wafer2.4.8 Maximum Force per Wafer; 2.4.9 ContactMethod; 2.4.10 Contact Life; 2.4.11 Minimizing Costs for SDBs and Contactors; 2.4.12 Bumped Wafers VersusWafers with Bond Pads; 2.4.13 Pitch; 2.4.14 Pad Size; 2.4.15 Coplanarity; 2.4.16 Background (Thinned) Wafers and Plastic-BackedWafers; 2.4.17 More Than One Die Type on theWafer; 2.4.18 Changing Cartridges; 2.4.19 Test Electronics; 2.4.20 Die Power and Shorted Die; 2.4.21 Current per Die and perWafer; 2.4.22 Voltage Levels Needed; 2.4.23 Clock and Pattern Frequencies; 2.4.24 WaferMaps and Binning.
- 2.5 FUTURE PROJECTIONSReferences; Chapter 3 Resource-Constrained Testing of Core-Based SoCs; 3.1 DEFECT PROBABILITY ESTIMATION FOR EMBEDDED CORES; 3.1.1 Unified Negative-BinomialModel for Yield Estimation; 3.1.2 Procedure to Determine Core Defect Probabilities; 3.2 TEST-LENGTH SELECTION FORWAFER-LEVEL TEST; 3.2.1 Test-Length Selection Problem:PTLS; 3.2.2 Efficient Heuristic Procedure; 3.2.3 Greedy Heuristic Procedure; 3.3 EXPERIMENTAL RESULTS; 3.3.1 Approximation Error in PrS Due to Taylor Series Approximation; 3.4 TEST DATA SERIALIZATION; 3.4.1 Test-Length and TAM Optimization Problem:PTLTWS.
- 3.4.2 Experimental Results:PTLTWS3.4.3 Enumeration-Based TAMWidth and Test-Length Selection; 3.4.4 TAMWidth and Test-Length Selection Based on Geometric Programming; 3.4.5 Approximation Error in PrS; 3.5 SUMMARY; References; Chapter 4 Defect Screening for "Big-D/Small-A"Mixed-Signal SoCs; 4.1 TEST WRAPPER FOR ANALOG CORES; 4.1.1 Analog Test Wrapper Modes; 4.2 WAFER-LEVEL DEFECT SCREENING: MIXED-SIGNAL CORES; 4.2.1 Signature Analysis: Mean-Signature-Based Correlation (MSBC); 4.2.2 Signature Analysis: Golden-Signature-Based Correlation (GSBC); 4.3 GENERIC COST MODEL.